Isolation structure and semiconductor device including the isolation structure

ABSTRACT

An isolation structure capable of preventing deterioration of breakdown voltage of a semiconductor device is obtained. The isolation structure, positioned between first and second conductive regions formed on a major surface of a semiconductor substrate for electrically insulating the first and second conductive regions from each other, includes a first conductor formed on a position deeper than the major surface of the semiconductor substrate, an insulator positioned in a direction opposite to that of the position of the first conductive region as viewed from the first conductor and formed on a position deeper than the major surface of the semiconductor substrate and a second conductor positioned in a direction opposite to that of the position of the first conductor as viewed from the insulator and formed on a position deeper than the major surface of the semiconductor substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This application is related to the co-pending U.S. patent applicationSer. No. 08/977,622 submitted on Nov. 25, 1997.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an isolation structure and asemiconductor device including the isolation structure, and morespecifically, it relates to an isolation structure capable ofsuppressing electric field concentration and a semiconductor deviceincluding the isolation structure.

2. Description of the Prior Art

In general, a p-channel LIGBT (lateral insulated gate bipolartransistor) formed on an SOI (silicon on insulator) substrate is knownas one of semiconductor devices. This LIGBT is a MOS gate controlledpower device generally applied to an electric motor or the likerequiring a high voltage and a heavy current. FIG. 51 is a sectionalview showing a conventional p-channel LIGBT. With reference to FIG. 51,the structure of the conventional p-channel LIGBT is now described.

Referring to FIG. 51, the conventional p-channel LIGBT includes asemiconductor substrate 101, a buried oxide film 102, an n⁻-type SOIlayer 103, a p-channel MOS transistor 104, a p⁺-type emitter diffusionregion 105, an n-type emitter diffusion region 106, a p⁻-type diffusionregion 107, a p-type collector diffusion region 109, an n⁺-typecollector diffusion region 110, a gate insulator film 108, a field oxidefilm 111 a, first multi-field plates 112 a to 112 c, second multi-fieldplates 114 a to 114 d, an emitter electrode 116 and a collectorelectrode 117.

The buried oxide film 102 is formed on the semiconductor substrate 101.The n⁻-type SOI layer 103 is formed on the buried oxide film 102. Thep⁺-type emitter diffusion region 105, the n-type emitter diffusionregion 106, the p⁻-type diffusion region 107, the p-type collectordiffusion region 109 and the n⁺-type collector diffusion region 110 areformed on prescribed regions of the SOI layer 103. The field oxide film111 a is formed on a major surface of the SOI layer 103 in a regionpositioned on the p⁻-type diffusion region 107. The gate insulator film108 is formed on the major surface of the SOI layer 103. The gateelectrode 120 is formed on the gate insulator film 108. The p⁺-typeemitter diffusion region 105, the p⁻-type diffusion region 107, the gateinsulator film 108 and the gate electrode 120 form the p-channel MOStransistor 104. The p-type collector diffusion region 109 is formed tobe in contact with the p⁻-type diffusion region 107. The firstmulti-field plates 112 a to 112 c consisting of conductor films of dopedpolysilicon or the like are formed on the major surface of the SOI layer103 and the field oxide film 111 a. An interlayer insulator film 113 isformed on the first multi-field plates 112 a to 112 c and the gateelectrode 120. The second multi-field plates 114 a to 114 d are formedon the interlayer insulator film 113 by aluminum wires or the like. Theemitter electrode 116 is formed to be electrically connected with thep⁺-type emitter diffusion region 105 and the n-type emitter diffusionregion 106. The collector electrode 117 is formed to be electricallyconnected with the p-type collector diffusion region 109 and the n⁺-typecollector diffusion region 110. A glass-coated insulator film 115 isformed on the emitter electrode 116, the collector electrode 117 and thesecond multi-field plates 114 a to 114 d. A trench isolation structure118 including a field oxide film 111 b is formed to be adjacent to thep-type collector diffusion region 109. A back electrode 121 is formedalong the overall back surface of the semiconductor substrate 101.

The LIGBT having the sectional structure shown in FIG. 51 is formedsymmetrically about a centerline 119, and has a substantially circularlayout as shown in FIG. 52, for example. FIG. 52 is a partiallyfragmented perspective view of an exemplary conventional LIGBT. Whilethe LIGBT shown in FIG. 52 has a circular layout, the layout of such anLIGBT is not restricted to the circular one but may be a square orrectangular one symmetrical about the centerline 119.

An OFF operation of the conventional LIGBT shown in FIG. 51 is nowdescribed with reference to FIG. 53. FIG. 53 is a typical sectional viewfor illustrating the OFF operation of the conventional LIGBT.

Referring to FIG. 53, the emitter electrode 116 is connected to a powersource having a positive potential (+V) in the OFF operation of theconventional LIGBT. The gate electrode 120 is set at the same level as apower supply potential. The collector electrode 117 and the backelectrode 121 are grounded and maintain a ground potential.

In this potential state, a depletion layer extends from a p-n junctionpart of a boundary surface J1 between the p⁻-type diffusion region 107and the p-type collector diffusion region 109 and the n⁻-type SOI layer103 toward the n⁻-type SOI layer 103. A first potential 122 is formed inthe extending depletion layer. This is called a RESURF (reduced surface)effect, which is a basic technique employed for improving breakdownvoltage of a lateral device.

In the conventional LIGBT, sharing of voltage load between the siliconand oxide films in the vertical direction is decided in response to theratio between the dielectric constants thereof. In the transversedirection, on the other hand, the first and second multi-field plates112 a to 112 c and 114 a to 114 d attain electric field relaxation. Inother words, the first and second multi-field plates 112 a to 112 c and114 a to 114 d homogenize the profile of the first potential 122 in thedevice surface area by capacitive coupling formed by the insulator andconductor films (this function is hereinafter referred to capacitivepotential division). Consequently, it is possible to suppress occurrenceof an avalanche phenomenon caused by electric field concentrationresulting from local heterogeneity of the first potential 122.

Thus, no voltage load is applied to the trench isolation structure 118in the OFF operation of the conventional LIGBT. As shown in FIG. 54, themain function of the trench isolation structure 118 is to bear a secondpotential 125 generated when an external potential (V_(EX)) is suppliedto an external region 123 for maintaining isolation between the deviceand the external region 123. FIG. 54 is a typical sectional view forillustrating the function of the trench isolation structure 118.

When the aforementioned LIGBT is applied to a high-side driver for aone-chip invertor, for example, the current drivability of the LIGBTmust be improved, i.e., the amount of a feedable current must beincreased. As a method for improving the current dlivability, it iseffective to increase the channel width (peripheral length) of the gateelectrode 120 (see FIG. 51). In order to increase the peripheral lengthof the gate electrode 120, the emitter electrode 116 and the collectorelectrode 117 of the LIGBT may be reversely arranged as shown in FIG.55. FIG. 55 is a sectional view showing an LIGBT having reverselyarranged emitter and collector electrodes 116 and 117. Referring to FIG.55, a gate electrode 120 is formed on a position separated from acenterline 119 as compared with that shown in FIG. 51, due to thereverse arrangement of the emitter electrode 116 and the collectorelectrode 117. When the LIGBT is formed in a circular layout symmetricalabout the centerline 119, therefore, the peripheral length of the gateelectrode 120 can be increased as compared with that shown in FIG. 51.When the LIGBT is turned on, therefore, a larger amount of Hall currentcan be fed from the emitter electrode 116 to the collector electrode 117through a p-channel MOS transistor 104.

When the emitter electrode 116 and the collector electrode 117 arereversely arranged as shown in FIG. 55, however, breakdown voltage isdisadvantageously reduced in an OFF operation. This problem is nowdescribed with reference to FIG. 56. FIG. 56 is a typical sectional viewfor illustrating the OFF operation of the LIGBT shown in FIG. 55.

Referring to FIG. 56, the emitter electrode 116 is connected to a powersource having a positive potential (+V) and the gate electrode 120 ismaintained at the same level as a power supply potential in the OFFoperation of the LIGBT, similarly to that shown in FIG. 53. Thecollector electrode 117 and a back electrode 121 are grounded tomaintain a ground potential. In such a potential state, extension of adepletion layer in an n⁻-type SOI layer 103 and a potential profile arebasically reverse to those in the OFF operation of the conventionalLIGBT shown in FIG. 53. In the LIGBT, therefore, first and secondmulti-field plates 112 a to 112 c and 114 a to 114 d keep conditions formaintaining breakdown voltage due to electric field relaxation and aRESURF effect.

In the OFF operation of the LIGBT shown in FIG. 55, however, a thirdpotential 126 penetrates a trench isolation structure 118, as shown inFIG. 56. In this case, electric field concentration may locally takeplace on a boundary region between the trench isolation structure 118and the n⁻-type SOI layer 103 since no structure is provided forsuppressing electric field concentration over a region positioned underthe emitter electrode 116 and the trench isolation structure 118. Suchelectric field concentration results in an avalanche phenomenon, leadingto reduction of the breakdown voltage in the OFF operation of the LIGBT.

In general, therefore, it is difficult to freely change the layout ofthe electrodes in the LIGBT, due to the reduction of the breakdownvoltage.

SUMMARY OF THE INVENTION

An object of the present invention is to provide an isolation structurewhich can prevent a semiconductor device from deterioration of breakdownvoltage.

Another object of the present invention is to provide a semiconductordevice which can prevent deterioration of breakdown voltage also whenthe layout such as the arrangement of electrodes is changed.

An isolation structure according to a first aspect of the presentinvention for isolating a first conductive region and a secondconductive region formed on a major surface of a semiconductor substratefrom each other includes a potential regulator. The potential regulatoris formed on a position deeper than the major surface of thesemiconductor substrate, for reducing a potential in an electric fieldstepwise when the electric field is formed between the first conductiveregion and the second conductive region.

Therefore, local electric field concentration can be effectivelyprevented on the position deeper than the major surface of thesemiconductor substrate. Consequently, it is possible to prevent theisolation structure from reduction of breakdown voltage resulting fromelectric field concentration.

In the isolation structure according to the first aspect of the presentinvention, the potential regulator may include a first conductor, aninsulator and a second conductor. The first conductor may be formed on aposition deeper than the major surface of the semiconductor substrate.The insulator may be formed on a region positioned in a directionopposite to that of the position of the first conductive region asviewed from the first conductor, and the second conductor may be formedon a region positioned in a direction opposite to that of the positionof the first conductor as viewed from the insulator.

In this case, the first and second conductors and the insulator can forma capacitance. If an electric field is formed between the firstconductive region and the second conductive region, an equipotentialsurface can be formed along a surface of the insulator due to thecapacitance formed by the first and second conductors and the insulator.Consequently, the position of the equipotential surface can becontrolled for preventing local electric field concentration in theisolation structure.

In the isolation structure according to the first aspect of the presentinvention, the first and second conductors and the insulator may beformed in a trench formed on the semiconductor substrate.

In the isolation structure according to the first aspect of the presentinvention, first and second trenches having side walls may be formed onthe semiconductor substrate in a region between the first conductiveregion and the second conductive region, and the insulator may be formedon the side walls of the first and second trenches. The first conductormay be formed on the insulator in the first trench, and the secondconductor may be formed on the insulator in the second trench.

An isolation structure according to a second aspect of the presentinvention, positioned between a first conductive region and a secondconductive region formed on a major surface of a semiconductor substratefor electrically isolating the first conductive region and the secondconductive region from each other, includes a first conductor, aninsulator and a second conductor. The first conductor is formed on aposition deeper than the major surface of the semiconductor substrate.The insulator is positioned in a direction opposite to that of theposition of the first conductive region as viewed from the firstconductor and formed on a position deeper than the major surface of thesemiconductor substrate. The second conductor is positioned in adirection opposite to that of the position of the first conductor asviewed from the insulator and formed on a position deeper than the majorsurface of the semiconductor substrate.

Therefore, a capacitance consisting of the first conductor, theinsulator and the second conductor can be formed on a position deeperthan the major surface of the semiconductor substrate between the firstand second conductive regions. Also when a voltage is applied to thefirst and second conductive regions and an electric field is formedbetween the first and second conductive regions, therefore, anequipotential surface can be formed along a surface of the insulatorfilm due to the capacitance formed by the first and second conductorsand the insulator. Therefore, the position of the equipotential surfacecan be controlled by adjusting the positions of the first and secondconductors and the insulator in a region deeper than the major surfaceof the semiconductor substrate. Consequently, local electric fieldconcentration can be prevented.

In the isolation structure according to the second aspect of the presentinvention, the first and second conductors and the insulator may beformed in a trench formed on the semiconductor substrate.

In the isolation structure according to the second aspect of the presentinvention, first and second trenches having side walls may be formed onthe semiconductor substrate in a region between the first conductiveregion and the second conductive region, and the insulator may be formedon the side walls of the first and second trenches. The first conductormay be formed on the insulator in the first trench, and the secondconductor may be formed on the insulator in the second trench.

According to the second aspect of the present invention, the isolationstructure may further include an isolation insulator film, first andsecond field plate conductor films and a separation insulator film. Theisolation insulator film may be formed on the major surface of thesemiconductor substrate in a region positioned on the first and secondconductors and the insulator, and the first field plate conductor filmmay be formed on the isolation insulator film. The second field plateconductor film may be formed on the isolation insulator film on aposition close to the second conductor region from the first field plateconductor film at a space, and the separation insulator film may beformed between the first and second field plate conductor films.

Thus, the first and second field plate conductor films and theseparation insulator film can form a capacitance on a region positionedon the major surface of the semiconductor substrate. Also when a voltageis applied to the first and second conductive regions and an electricfield is formed between the first and second conductive regions,therefore, an equipotential surface can be formed along a surface of theseparation insulator film due to the capacitance formed by the first andsecond field plate conductor films and the separation insulator film.Thus, the position of the equipotential surface can be controlled byadjusting the positions of the first and second field plate conductorfilms and the separation insulator film on the isolation insulator film.In addition, the position of the equipotential surface can be furtherreliably controlled by the capacitance formed by the first and secondconductors and the insulator on the region deeper than the major surfaceof the semiconductor substrate and that formed by the first and secondfield plate conductor films and the separation insulator film on theisolation insulator film. Consequently, local electric fieldconcentration can be more reliably prevented.

In the isolation structure according to the second aspect of the presentinvention, the first field plate conductor film may be electricallyconnected with the first conductive region through a resistive element,the second field plate conductor film may be electrically connected withthe second conductive region through a resistive element, and the firstand second field plate conductive films may be electrically connectedwith each other through a resistive element.

Therefore, the potentials of the first and second field plate conductorfilms can be decided by regulating the voltage applied to the first andsecond conductive regions and the resistance values of the resistiveelements. Thus, the potential of the equipotential surface formed alongthe surface of the separation insulator film can be reliably decided(this function is hereinafter referred to as resistive potentialdivision). Consequently, the position of the equipotential surface canbe reliably controlled also when conductive foreign matter adheres to aportion around the isolation insulator film on the semiconductorsubstrate in a step of forming the first and second field plateconductor films or the like, the separation insulator film is locallyheterogeneously formed or electrical noise is externally applied to theisolation structure, thereby reliably preventing electric fieldconcentration.

The potentials of the first and second field plate conductor films canbe regulated by adjusting the resistance values of the resistiveelements or the like, thereby increasing the degree of freedom for thelayout of the first and second field plate conductor films, theseparation insulator film and the like.

According to the second aspect of the present invention, the isolationstructure may further include an interlayer insulator film, third andfourth field plate conductor films and an upper insulator film. Theinterlayer insulator film may be formed on the first and second fieldplate conductor films, and the third field plate conductor film may beformed on the interlayer insulator film. The fourth field plateconductor film may be electrically insulated from the third fieldconductor film and formed at a space, and the upper insulator film maybe formed between the third and fourth field plate conductor films.

Therefore, the third and fourth field plate conductor films and theupper insulator film can form a capacitance on the interlayer insulatorfilm. The position of an equipotential surface formed along a surface ofthe upper insulator film can be controlled by adjusting the positions ofthe third and fourth field plate conductor films and the upper insulatorfilm. Consequently, local electric field concentration can be morereliably prevented.

Further, the isolation structure including the first and second fieldplate conductor films having the resistive potential dividing functionand the third and fourth field plate conductor films having thecapacitive potential dividing function can implement more properpotential division by adjusting load balance between the resistivepotential dividing function and the capacitive potential dividingfunction in consideration of restriction in layout of the first tofourth field plate conductor films and design conditions such as anallowed value for a leakage current.

According to the second aspect of the present invention, the isolationstructure may further include a lower insulator film formed under thesemiconductor substrate, and the first conductive region may be formedto be in contact with the lower insulator film.

When a voltage higher than that for the second conductive region isapplied to the first conductive region, therefore, an electric field canbe formed in the lower insulator film positioned under the firstconductive region since no semiconductor substrate region forming anelectric field is present under the first conductive region. Theinsulator film has a higher breakdown voltage value than that of thesemiconductor substrate, and hence it is possible to preventdeterioration of breakdown voltage and an insulated state can bemaintained against higher electric field strength.

Further, no electric field concentration takes place on a boundaryregion between the isolation structure and the semiconductor substratepositioned under the first conductive region dissimilarly to the priorart, whereby the isolation structure can reliably maintain breakdownvoltage.

In the isolation structure according to the second aspect of the presentinvention, the trench may have an upper surface and a lower surface, andthe upper surface may have a plane area smaller than that of the lowersurface. Further, first and second conductors may be formed on the lowersurface.

Therefore, the first and second conductors can be formed in the vicinityof a boundary region, which has readily caused electric fieldconcentration in the prior art, between a lower portion of the isolationstructure and the semiconductor substrate. Thus, electric fieldconcentration can be more reliably prevented on the boundary regionbetween the lower portion of the isolation structure and thesemiconductor substrate due to the resistive or capacitive potentialdividing function of the first and second conductors and the insulator.

According to the second aspect of the present invention, the isolationstructure may further include an isolation insulator film formed on themajor surface of the semiconductor substrate in a region positioned onthe trench. Further, an end portion of the upper surface of the trenchmay be positioned inward beyond that of the isolation insulator film,and an end portion of the lower surface of the trench may be positionedoutward beyond that of the isolation insulator film.

In the isolation structure according to the second aspect of the presentinvention, the trench may have an upper surface and a lower surface, theupper surface may have a plane area larger than that of the lowersurface, and first and second conductors may be formed on the lowersurface.

According to the second aspect of the present invention, the isolationstructure may further include third and fourth conductors and a sidewall insulator film. The third and fourth conductors may be formed onside surfaces of the trench, and the side wall insulator film may beformed between the third and fourth conductors.

Therefore, the third and fourth conductors and the side wall insulatorfilm can form a capacitance. Also when the first and second conductiveregions are formed on relatively shallow regions of the major surface ofthe semiconductor substrate and the equipotential surface of theelectric field formed by voltage application to the first and secondconductive regions extends into the semiconductor substrate, theposition of the equipotential surface extending into the semiconductorsubstrate can be adjusted by the capacitance formed by the third andfourth conductors and the side wall insulator film. Consequently,electric field concentration in the semiconductor substrate can beprevented.

In the isolation structure according to the second aspect of the presentinvention, the first conductor may be electrically connected with thefirst conductive region through a resistive element, and the secondconductor may be electrically connected with the second conductiveregion through a resistive element. Further, the first conductor and thesecond conductor may be electrically connected with each other through aresistive element.

Therefore, the potentials of the first and second conductors can bedecided from the voltage applied to the first and second conductiveregions and the resistance values of the resistive elements, and thefirst and second conductors can be provided with a resistive potentialdividing function. Thus, local electric field concentration can be morereliably prevented.

Also when the positions for forming the first and second conductors arechanged, the potentials of the first and second conductors can bearbitrarily decided by regulating the voltage applied to the first andsecond conductive regions and the resistance values of the resistiveelements, thereby increasing the degree of freedom for the design of thefirst and second conductors.

An isolation structure according to a third aspect of the presentinvention, positioned between a first conductive region and a secondconductive region formed on a major surface of a semiconductor substratefor isolating the first conductive region and the second conductiveregion from each other, includes a resistive field plate structure and acapacitive field plate structure. The resistive field plate structureand the capacitive field plate structure are stacked with each otherthrough an interlayer insulator film.

The resistive field plate structure includes first and second fieldplate conductor films. The first field plate conductor film is formedbetween the first conductive region and the second conductive region andelectrically connected with the first conductive region through aresistive element. The second field plate conductor film is electricallyconnected with the first field plate conductor film and the secondconductor region through resistive elements respectively and formed at aspace in a direction along the position of the second conductive regionas viewed from the first field plate conductor film.

The capacitive field plate structure includes third and fourth fieldplate conductor films and an insulator film. The third field plateconductor film is formed between the first conductive region and thesecond conductive region. The fourth field plate conductor film iselectrically insulated from the third field plate conductor film andformed at a space. The insulator film is formed between the third fieldplate conductor film and the fourth field plate conductor film.

Thus, the isolation structure includes the resistive field platestructure and the capacitive field plate structure having differentcharacteristics. Even if characteristics required to the isolationstructure change in various ways, therefore, an isolation structureresponsive to the required characteristics can be readily obtained.

In the resistive field plate structure, the potentials of the first andsecond field plate conductor films are decided from a voltage applied tothe first and second conductive regions and the resistance values of theresistive elements and not influenced even if the layout of the firstand second field plate conductor films is changed. Thus, the degree offreedom for the layout of the first and second field plate conductorfilms can be increased. In the capacitive field plate structure, on theother hand, the third and fourth field plate conductor films areelectrically insulated from each other not to electrically connect thefirst and second conductive regions with each other, whereby a leakagecurrent between the first and second conductive regions can besubstantially zeroed. Thus, the isolation structure can readilyimplement various characteristics due to the provision of the two typesof field plate structures having different characteristics.

A semiconductor device according to a fourth aspect of the presentinvention includes an isolation structure, positioned between a firstconductive region and a second conductive region formed on a majorsurface of a semiconductor substrate for electrically isolating thefirst conductive region and the second conductive region from eachother, includes the isolation structure having first and secondconductors and an insulator. The first conductor is formed on a positiondeeper than the major surface of the semiconductor substrate. Theinsulator is positioned in a direction opposite to that of the positionof the first conductive region as viewed from the first conductor and isformed on a position deeper than the major surface of the semiconductorsubstrate. The second conductor is positioned in a direction opposite tothat of the position of the first conductor as viewed from the insulatorand formed on a position deeper than the major surface of thesemiconductor substrate.

Also when an electric field is formed between the first and secondconductive regions, therefore, an equipotential surface can be formedalong a surface of the insulator due to a capacitance formed by thefirst and second conductors and the insulator. The position of theequipotential surface can be controlled by adjusting the positions ofthe first and second conductors and the insulator, whereby localelectric field concentration can be prevented.

According to the fourth aspect of the present invention, thesemiconductor device may further include a first element including thefirst conductive region and a second element including the secondconductive region, the first element may be a circumferentially formedinsulated gate bipolar transistor including an emitter electrode and acollector electrode, and the isolation structure may be formed toenclose the insulated gate bipolar transistor. The emitter electrode maybe formed on a region closer to the outer periphery of thecircumferentially formed insulated gate bipolar transistor than thecollector electrode.

The insulated gate bipolar transistor is a power device applied to anelectric motor or the like requiring high voltage and a heavy current,and high breakdown voltage is required to the isolation structureapplied to such an insulated gate bipolar transistor. When the isolationstructure according to the present invention is applied to such aninsulated gate bipolar transistor, therefore, a particularly remarkableeffect can be attained.

The isolation structure has a potential dividing function formed by thefirst and second conductors and the insulator, whereby electric fieldconcentration can be prevented although the emitter electrode of theinsulated gate bipolar transistor is formed on the region closer to theouter periphery of the insulated gate bipolar transistor than thecollector electrode. Thus, the degree of freedom for arrangement of theemitter electrode and the collector electrode of the insulated gatebipolar transistor can be increased.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view showing a semiconductor device according toan embodiment 1 of the present invention;

FIG. 2 is a partially fragmented perspective view showing the overallsemiconductor device shown in FIG. 1;

FIG. 3 is a partially enlarged sectional view of the semiconductordevice shown in FIG. 1;

FIG. 4 is a typical sectional view for illustrating an OFF operation ofthe semiconductor device shown in FIG. 1;

FIGS. 5 to 9 are sectional views for illustrating first to fifth stepsfor fabricating the semiconductor device shown in FIG. 3;

FIG. 10 is a partially enlarged sectional view showing a modification ofthe semiconductor device according to the embodiment 1 of the presentinvention;

FIGS. 11 to 17 are sectional views for illustrating first to seventhsteps for fabricating the semiconductor device shown in FIG. 10;

FIG. 18 is a partially enlarged sectional view showing a semiconductordevice according to an embodiment 2 of the present invention;

FIG. 19 is a typical sectional view for illustrating an OFF operation ofthe semiconductor device shown in FIG. 18;

FIG. 20 is a typical plan view showing a semiconductor device accordington an embodiment 3 of the present invention;

FIG. 21 is a typical sectional view taken along the line 100—100 in FIG.20;

FIG. 22 is a partially enlarged sectional view showing a semiconductordevice according to an embodiment 4 of the present invention;

FIG. 23 is a typical sectional view for illustrating an OFF operation ofthe semiconductor device shown in FIG. 22;

FIGS. 24 to 31 are sectional views for illustrating first to eighthsteps for fabricating the semiconductor device shown in FIG. 22;

FIG. 32 is a partially enlarged sectional view showing a semiconductordevice according to an embodiment 5 of the present invention;

FIGS. 33 to 38 are sectional views for illustrating first to sixth stepsfor fabricating the semiconductor device shown in FIG. 32;

FIG. 39 is a partially enlarged sectional view showing a semiconductordevice according to an embodiment 6 of the present invention;

FIGS. 40 to 43 are sectional views for illustrating first to fourthsteps for fabricating the semiconductor device shown in FIG. 39;

FIG. 44 is a partially enlarged sectional view showing a semiconductordevice according to an embodiment 7 of the present invention;

FIG. 45 is a typical sectional view for illustrating an OFF operation ofthe semiconductor device shown in FIG. 44;

FIGS. 46 to 50 are sectional views for illustrating first to fifth stepsfor fabricating the semiconductor device shown in FIG. 44;

FIG. 51 is a sectional view showing a conventional semiconductor device;

FIG. 52 is a partially fragmented perspective view showing the overallsemiconductor device shown in FIG. 51;

FIG. 53 is a typical sectional view for illustrating an OFF operation ofthe conventional semiconductor device shown in FIG. 51;

FIG. 54 is a typical sectional view for illustrating the function of atrench isolation structure of the conventional semiconductor deviceshown in FIG. 51;

FIG. 55 is a sectional view showing an LIGBT having reversely arrangedemitter and collector electrodes; and

FIG. 56 is a typical sectional view for illustrating an OFF operation ofthe LIGBT shown in FIG. 55.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention are now described with reference tothe drawings.

(Embodiment 1)

Referring to FIG. 1, the semiconductor device is a p-channel LIGBTincluding a trench isolation structure 18, a p⁺-type emitter diffusionregion 5, an n-type emitter diffusion region 6, a p⁻-type diffusionregion 7, a p-type collector diffusion region 9, an n⁺-type collectordiffusion region 10, a gate insulator film 8, a gate electrode 20, anemitter electrode 16, a collector electrode 17, first multi-field plates12 a to 12 c and second multi-field plates 14 a to 14 d.

A buried oxide film 2 is formed on a semiconductor substrate 1. Ann⁻-type SOI layer 3 is formed on the buried oxide film 2. The p⁺-typeemitter diffusion region 5, the n-type emitter diffusion region 6, thep⁻-type diffusion region 7, the p-type collector diffusion region 9 andthe n⁺-type collector diffusion region 10 are formed on a major surfaceof the SOI layer 3. A field oxide film 11 a is formed on the majorsurface of the SOI layer 3. The gate electrode 20 is formed on the majorsurface of the SOI layer 3 through the gate insulator film 8. The gateelectrode 20, the gate insulator film 8, the p⁺-type emitter diffusionregion 5 and the p⁻-type diffusion region 7 form a p-channel MOStransistor 4. The first multi-field plates 12 a to 12 c are formed onthe major surface of the SOI layer 3 and the field oxide film 11 a. Aninterlayer insulator film 13 a is formed on the first multi-field plates12 a to 12 c. The emitter electrode 16 is formed to be in contact withthe p⁺-type emitter diffusion region 5 and the n-type emitter diffusionregion 6 while extending on the interlayer insulator film 13 a. Thecollector electrode 17 is formed to be in contact with the p-typecollector diffusion region 9 and the n⁺-type collector diffusion region10 while extending on the interlayer insulator film 13 a. The secondmulti-field plates 14 a to 14 d are formed on the interlayer insulatorfilm 13 a. A glass-coated insulator film 15 is formed on the secondmulti-field plates 14 a to 14 d. The trench isolation structure 18isolates the device region formed with the p-channel LIGBT from anexternal region 23.

The p-channel LIGBT having such a structure is substantiallycircumferentially formed about a centerline 19, as shown in FIG. 2. Thetrench isolation structure 18 is formed to enclose the p-channel LIGBT.A back electrode 21 is formed on a back surface of the semiconductorsubstrate 1.

The trench isolation structure 18 is now described with reference toFIG. 3.

Referring to FIG. 3, the trench isolation structure 18 includes trenchside wall insulator films 28 a to 28 f formed in trenches 47 a to 47 c,polysilicon buried films 29 a to 29 c, a field oxide film 11 b, thirdmulti-field plates 30 a to 30 d and fourth multi-field plates 32 a to 32c.

The trenches 47 a to 47 c are formed in the SOI layer 3. The trench sidewall insulator films 28 a to 28 f are formed on side walls of thetrenches 47 a to 47 c. The polysilicon buried films 29 a to 29 c areformed on the trench side wall insulator films 28 a to 28 f, to fill upthe trenches 47 a to 47 c. The polysilicon buried films 29 a to 29 c aremade of doped polysilicon or non-doped polysilicon.

The field oxide film 11 b is formed on the major surface of the SOIlayer 3 in a region positioned on the trenches 47 a to 47 c. The thirdmulti-field plates 30 a to 30 d are formed on the major surface of theSOI layer 3 and the field oxide film 11 b. Insulator thin films 31 a and31 b are formed between the multi-field plates 30 a and 30 d and the SOIlayer 3 respectively. The third multi-field plates 30 a to 30 d are madeof a conductor such as doped polysilicon, similarly to the firstmulti-field plates 12 a to 12 c (see FIG. 1). The dimensional patternsof the third multi-field plates 30 a to 30 d correspond to the openingpatterns of the trenches 47 a to 47 c. The third multi-field plates 30 ato 30 d are formed on regions positioned between the trenches 47 a to 47c respectively.

An interlayer insulator film 13 b is formed on the third multi-fieldplates 30 a to 30 d. The fourth multi-field plates 32 a to 32 c and aterminal component 33 therefor are formed on the interlayer insulatorfilm 13 b. The dimensional patterns of the fourth multi-field plates 32a to 32 c correspond to the patterns of the third multi-field plates 30a to 30 d. The fourth multi-field plates 32 a to 32 c are formed onregions positioned between the third multi-field plates 30 a to 30 drespectively.

The terminal component 33 for the fourth multi-field plates 32 a to 32 cis electrically connected with the external region 23. The fourthmulti-field plates 32 a to 32 c and the terminal component 33 thereforare made of aluminum or the like, similarly to the emitter electrode 16.A glass-coated insulator film (not shown) is formed on the fourthmulti-field plates 32 a to 32 c.

An OFF operation of the semiconductor device is now described withreference to FIG. 4.

Referring to FIG. 4, the emitter electrode 16 is connected to a powersource having a positive potential (+V) in the OFF operation of thesemiconductor device. The gate electrode 20 is maintained at the samelevel as a power supply potential. The back electrode 21 and thecollector electrode 17 (see FIG. 1) are grounded and maintain a groundpotential. The external region 23 and the terminal component 33 for thefourth multi-field plates 32 a to 32 c are supplied with the groundpotential. A potential 34 generated in such a potential state is firstrelaxed to have a substantially homogeneous profile due to a capacitivepotential dividing action of the fourth multi-field plates 32 a to 32 c.Further, the potential 34 is also relaxed by a capacitive potentialdividing action of the third multi-field plates 30 a to 30 d to haveuniform profile. The dimensional patterns of the third multi-fieldplates 30 a to 30 d correspond to those of the trenches 47 a to 47 cforming the trench isolation structure 18. Therefore, the potential 34divided by the third multi-field plates 30 a to 30 d is substantiallyhomogeneously distributed to the trench side wall insulator films 28 ato 28 f formed in the trenches 47 a to 47 c. The potential 34 isconnected with a potential formed by a RESURF effect in the device bodyin the buried oxide film 2. This is because the potential 34 extendsfrom the region provided with the third multi-field plates 30 a to 30 dand fourth multi-field plates 32 a to 32 c in the substantiallyhomogeneous profile state into the buried oxide film 2 along the trenchside wall insulator films 28 a to 28 f.

Consequently, local electric field concentration, which has beendisadvantageously caused in the prior art, can be prevented in a region27 close to the interface between the trench isolation structure 18 andthe SOI layer 3. Thus, the semiconductor device can be effectivelyprevented from reduction of breakdown voltage resulting from electricfield concentration.

Thus, local electric field concentration can be prevented in the region27 close to the interface, whereby prescribed breakdown voltage can beobtained in the OFF operation although the emitter electrode 16 and thecollector electrode 17 of the p-channel LIGBT are arranged reversely tothose of the prior art as shown in FIG. 1. Consequently, the degree offreedom can be improved as compared with the prior art in relation tothe layout of the emitter electrode 16 and the collector electrode 17 ofthe p-channel LIGBT.

Steps for fabricating the semiconductor device are now described withreference to FIGS. 5 to 9.

Referring to FIG. 5, the buried oxide film 2 is formed on thesemiconductor substrate (not shown). The n⁻-type SOI layer 3 is formedon the buried oxide film 2. A resist pattern 46 is formed on the SOIlayer 3.

Then, the resist pattern 46 is employed as a mask for partially removingthe SOI layer 3 by etching, thereby forming the trenches 47 a to 47 c(see FIG. 6). Thereafter the resist pattern 46 is removed. Thus, thestructure shown in FIG. 6 is obtained.

Then, insulator films 28 a to 28 f for defining the trench side wallinsulator films are formed on the SOI layer 3 and in the trenches 47 ato 47 c, as shown in FIG. 7. A polysilicon film 48 is formed on theinsulator films 28 a to 28 f.

Then, parts of the insulator films 28 a to 28 f positioned on the SOIlayer 3 and the polysilicon film 48 are removed by etching, as shown inFIG. 8. Thus, the polysilicon buried films 29 a to 29 c are formed inthe trenches 47 a to 47 c.

Then, the field oxide film 11 b is formed on the surface of the SOIlayer 3 in the region positioned on the trenches 47 a to 47 c, as shownin FIG. 9.

Thereafter the third multi-field plates 30 a to 30 d, the fourthmulti-field plates 32 a to 32 c and the like are formed on the fieldoxide film 11 b through a step similar to a conventional step forforming the first and second multi-field plates 12 a to 12 c and 14 a to14 d. Thus, the semiconductor device shown in FIG. 3 can be obtained.

Another semiconductor device is now described with reference to FIG. 10.

Referring to FIG. 10, the semiconductor device includes a trenchisolation structure 18 for isolating a p-channel LIGBT from an externalregion 23 similarly to the semiconductor device shown in FIG. 3, and thep-channel LIGBT formed adjacently to the trench isolation structure 18is basically similar in structure to the p-channel LIGBT shown in FIG.1. Further, the trench isolation structure 18 formed on a surface of aSOI layer 3 is basically similar in structure to the isolation structure18 shown in FIG. 3. In the semiconductor device shown in FIG. 10,however, the trench isolation structure 18 includes trenches 50 a to 50f formed on upper and lower surfaces of the SOI layer 3 and p⁺-typediffusion regions 49 a and 49 b for electrically isolating the deviceregion provided with the p-channel LIGBT from the external region 23.Insulator films 51 a to 51 c and 55 a to 55 c are formed in the trenches50 a to 50 f. Polysilicon buried films 52 a to 52 f are formed on theinsulator films 51 a to 51 c and 55 a to 55 c, to fill up the trenches50 a to 50 f.

Therefore, the polysilicon buried films 52 a to 52 f and the insulatorfilms 51 a to 51 c and 55 a to 55 c act as capacitances in an OFFoperation of the p-channel LIGBT for forming equipotential surfacesalong the insulator films 51 a to 51 c and 55 a to 55 c formed on theside walls of the trenches 50 a to 50 f, whereby an effect similar tothat of the trench isolation structure 18 of the semiconductor deviceshown in FIG. 3 can be attained.

Steps for fabricating the semiconductor device are now described withreference to FIGS. 11 to 17.

As shown in FIG. 11, a resist pattern (not shown) is first formed on alower surface of a semiconductor substrate 3 (hereinafter referred to asthe SOI layer 3) for defining the n⁻-type SOI layer 3. The resistpattern is employed as a mask for partially removing the SOI layer 3 byanisotropic etching, thereby forming the trenches 50 a to 50 c.Thereafter the resist pattern is removed.

Then, an insulator film 51 is formed on the lower surface of the SOIlayer 3 and in the trenches 50 a to 50 c, as shown in FIG. 12. Apolysilicon film 48 is formed on the insulator film 51.

Then, parts of the insulator film 51 and the polysilicon film 48positioned on the lower surface of the SOI layer 3 are removed byetching, as shown in FIG. 13.

Then, a semiconductor substrate (not shown) provided with a buried oxidefilm 2 is bonded to the lower surface of the SOI layer 3, as shown inFIG. 14. A resist pattern 53 is formed on an upper surface of the SOIlayer 3.

Then, the resist pattern 53 (see FIG. 14) is employed as a mask forpartially removing the SOI layer 3 by etching, thereby forming thetrenches 50 d to 50 f, as shown in FIG. 15. Thereafter the resistpattern 53 is removed.

Then, an insulator film 54 is formed on the upper surface of the SOIlayer 3 and in the trenches 50 d to 50 f, as shown in FIG. 16. Apolysilicon film 48 is formed on the insulator film 54.

Then, parts of the insulator film 54 and the polysilicon film 48positioned on the upper surface of the SOI layer 3 are removed byetching, as shown in FIG. 17. Thus, the insulator films 55 a to 55 c andthe polysilicon buried films 52 d to 52 f are formed in the trenches 50d to 50 f.

Thereafter p⁺-type diffusion regions 49 a and 49 b (see FIG. 10), afield oxide film 11 b and the like are formed thereby obtaining thesemiconductor device shown in FIG. 10.

(Embodiment 2)

Referring to FIG. 18, the semiconductor device is basically similar instructure to the semiconductor device according to the embodiment 1 ofthe present invention shown in FIG. 3. In the semiconductor device shownin FIG. 18, however, an n-type emitter diffusion region 6 is formed tobe in contact with a buried oxide film 2.

An action in an OFF operation of the semiconductor device shown in FIG.18 is described with reference to FIG. 19.

Referring to FIG. 19, the semiconductor device, having a trenchisolation structure 18 basically similar in structure to that of thesemiconductor device according to the embodiment 1 of the presentinvention shown in FIG. 3, can attain an effect similar to that of thesemiconductor device according to the embodiment 1. The n-type emitterdiffusion region 6 is formed to be in contact with the buried oxide film2, whereby a depletion layer formed in the body of a p-channel LIGBTcannot penetrate a region 27 close to the interface between the trenchisolation structure 18 and an SOI layer 3. On a portion under an emitterelectrode 16, therefore, a potential 35 is distributed as if pushed outfrom the SOI layer 3 to a buried oxide film 2. Therefore, local electricfield concentration can be more reliably prevented in the region 27close to the interface.

(Embodiment 3)

Referring to FIG. 20, the semiconductor device includes an integralspiral field plate structure 36 for an isolation structure 18 thereof. Adevice enclosed with the integral spiral field plate structure 36 is ap-channel LIGBT, similarly to the semiconductor device according to theembodiment 1 of the present invention. The trench isolation structure 18(see FIG. 21) is formed to enclose the p-channel LIGBT. The integralspiral field plate structure 36 is formed on the trench isolationstructure 18. Multi-field plates 32 a to 32 c (see FIG. 21) are formedon the integral spiral field plate structure 36, similarly to thesemiconductor device shown in FIG. 3.

The integral spiral field plate structure 36 is formed by a thinconductor film of high resistance such as a silicon film having a highnitrogen content, for example. An inner peripheral end of the integralspiral field plate structure 36 is electrically connected with anelectrode of the device body such as an emitter electrode 16 (see FIG.21) of the p-channel LIGBT, for example. On the other hand, an outerperipheral end of the integral spiral field plate structure 36 iselectrically connected with an external region 23 and maintained at aground potential in an OFF operation of the semiconductor device.

Thus, the integral spiral field plate structure 36 is formed by the thinconductor film of high resistance, whereby potentials on respectivepositions of integral spiral field plate structures 36 a to 36 d (seeFIG. 21) can be decided from the resistance value of the thin conductorfilm and the distances from the internal peripheral end of the integralspiral field plate structure 36. Also when a potential is formed in thetrench isolation structure 18 in the OFF operation of the semiconductordevice, therefore, the position of an equipotential surface thereof canbe forcibly fixed by the respective potentials of the integral spiralfield plate structures 36 a to 36 d (this function is hereinafterreferred to as resistive potential division). Even if conductive foreignmatter or the like is present in the vicinity of the integral spiralfield plate structures 36 a to 36 d, therefore, the position of theequipotential surface of the potential is hardly influenced. Even ifelectrical noise or the like is externally applied, further, theposition of the equipotential surface of the potential can be morestabilized as compared with multi-field plates such as the third andfourth multi-field plates 30 a to 30 d and 32 a to 32 c havingcapacitive potential dividing functions.

Further, multi-field plates 32 a to 32 c having a capacitive potentialdividing function are formed on the integral spiral field platestructures 36 a to 36 d having the resistive potential dividing functionthrough an insulator film (not shown). Thus, the semiconductor devicecan more reliably homogenize the potential profile as compared with thesemiconductor device according to the embodiment 1 of the presentinvention employing only the multi-field plates 30 a to 30 d and 32 a to32 c having the capacitive potential dividing function, due to theemployment of the field plate structures 36 a to 36 d having theresistive potential dividing function and the multi-field platestructures 32 a to 32 c having the capacitive potential dividingfunction.

While the multi-field plates 32 a to 32 c having the capacitivepotential dividing function hardly cause a leakage current since thedevice region therefor is insulated from the external region 23, thedegree of freedom for the layout thereof is relatively inferior to thatof the field plate structure 36 having the resistive potential dividingfunction. On the other hand, the integral spiral field plate structures36 a to 36 d having the resistive potential dividing function cause aleakage current since the device region therefor is not completelyinsulated from the external region 23 although the position of theequipotential surface can be controlled by adjusting the resistancevalue of the material therefor or the like and the degree of freedom forthe layout thereof can be increased. Thus, an isolation structureapplicable to various required characteristics can be readily obtainedby employing field plate structures having different characteristics.

Although an integral resistive field plate structure connected betweenelectrodes of a device for facilitating a RESURF effect in the devicehas been proposed (K. Endo, Y. Baba, Y. Udo, M. Yasui and Y. Sano, “A500 V 1A 1-Chip Inverter IC with a New Electric Field ReductionStructure” ISPSD 94, pp. 379-383 (1994)), there has been proposed nostructure connecting one main electrode of a device with an externalelectrode on a trench isolation structure.

(Embodiment 4)

Referring to FIG. 22, the semiconductor device is basically similar instructure to the semiconductor device shown in FIG. 18. In thissemiconductor device, however, an inverted V-shaped isolation structure37 is formed under a field oxide film 11 b. The inverted V-shapedisolation structure 37 includes side wall insulator films 38, a buriedinsulator film 39 and fifth multi-field plates 40 a to 40 f. The sidewall insulator films 38 are formed on side surfaces of a trench formedunder the field oxide film 11 b. The buried insulator film 39 is formedon the side wall insulator films 38, to fill up the trench. Trenches 44a to 44 f are formed on a lower surface of the buried insulator film 39.An insulator film 56 is formed on the lower surface of the buriedinsulator film 39 and in the trenches 44 a to 44 f. The fifthmulti-field plates 40 a to 40 f are formed by conductor films to fill upthe trenches 44 a to 44 f. The fifth multi-field plates 40 a to 40 f areelectrically insulated from each other, and have a capacitive potentialdividing function similarly to the first to fourth multi-field plates 12a to 12 c, 14 a to 14 d, 30 a to 30 d and 32 a to 32 c of thesemiconductor device according to the embodiment 1 of the presentinvention.

An OFF operation of the semiconductor device shown in FIG. 22 is nowdescribed with reference to FIG. 23.

Referring to FIG. 23, potential states of an emitter electrode 16, aback electrode 21 and the like are basically similar to those in the OFFoperation of the semiconductor device according to the embodiment 1 ofthe present invention shown in FIG. 4. The semiconductor device canattain an effect similar to that of the semiconductor device accordingto the embodiment 2 of the present invention, due to the capacitivepotential dividing function of the fifth multi-field plates 40 a to 40f. In the inverted V-shaped isolation structure 37, the buried insulatorfilm 39 has a lower surface wider than the upper surface, and hence thenumber of the fifth multi-field plates 40 a to 40 f can be increasedwithout changing the structure on the field oxide film 11 b. On thelower surface of the buried insulator film 39, therefore, anequipotential surface of a potential 41 can be divided into a largernumber, thereby more reliably preventing local electric fieldconcentration in a region 42 close to the interface between the invertedV-shaped isolation structure 37 and an SOI layer 3. Therefore,deterioration of breakdown voltage in the OFF operation of thesemiconductor device can be more reliably prevented.

Steps for fabricating the semiconductor device are now described withreference to FIGS. 24 to 31.

First, an inverted V-shaped trench is formed on a lower surface of theSOI layer 3 by anisotropic etching employing KOH or the like, as shownin FIG. 24. The lower surface of the SOI layer 3 and the internalsurface of the trench are thermally oxidized for forming a side wallinsulator film 38.

Then, an insulator film of BPSG or TEOS is deposited on the side wallinsulator film 38 and thereafter flattened for forming the buriedinsulator film 39, as shown in FIG. 25. The lower surface of the buriedinsulator film 39 is substantially flush with that of the side wallinsulator film 38 positioned on the lower surface of the SOI layer 3.

Then, a resist pattern 43 is formed on the lower surfaces of the sidewall insulator film 38 and the buried insulator film 39, as shown inFIG. 26. The resist pattern 43 is employed as a mask for partiallyremoving the buried insulator film 39 by anisotropic etching, therebyforming the trenches 44 a to 44 f.

Then, the resist pattern 43 (see FIG. 26) is removed and thereafter aninsulator film 56 is formed on the lower surface of the buried insulatorfilm 39 and in the trenches 44 a to 44 f, as shown in FIG. 27.

Then, a doped polysilicon film 45 is formed on the lower surface of theside wall insulator film 38 and on the insulator film 56, as shown inFIG. 28.

Then, a flattening step is carried out thereby forming the fifthmulti-field plates 40 a to 40 f, as shown in FIG. 29. At this time, thelower surface of the side wall insulator film 38 and those of the fifthmulti-field plates 40 a to 40 f are flattened to be substantially flushwith each other.

Then, a semiconductor substrate 1 provided with a buried oxide film 2 isbonded to the lower surface of the SOI layer 3, as shown in FIG. 30. Thebond strength is improved by heat treatment at a high temperature ofabout 1100 to 1200° C.

Then, the upper surface of the SOI layer 3 is polished for adjusting theSOI layer 3 to a prescribed thickness, as shown in FIG. 31.

Thereafter the field oxide film 11 b (see FIG. 22) and the like areformed to obtain the semiconductor device shown in FIG. 22.

(Embodiment 5)

Referring to FIG. 32, the semiconductor device is basically identical instructure to the semiconductor device according to the embodiment 4 ofthe present invention shown in FIG. 22. In the semiconductor deviceshown in FIG. 32, however, fifth multi-field plates 40 a to 40 f formedon a bottom portion of an inverted V-shaped isolation structure 37 havea resistive potential dividing function. The fifth multi-field plates 40a to 40 f are similar in plane shape to the integral spiral field platestructure 36 in the semiconductor device according to the embodiment 3shown in FIG. 20, and the multi-field plate 40 a corresponding to aninner peripheral end of the fifth multi-field plates 40 a to 40 f iselectrically connected with an n-type emitter diffusion region 6. Themulti-field plate 40 f corresponding to an outer peripheral end of thefifth multi-field plates 40 a to 40 f is electrically connected with anexternal region 23. The fifth multi-field plates 40 a to 40 f are madeof a conductor of high resistance such as silicon having a high nitrogencontent, for example.

Therefore, the semiconductor device shown in FIG. 32 can attain aneffect similar to that of the integral spiral field plate structures 36a to 36 d of the semiconductor device according to the embodiment 3 ofthe present invention, in addition to an effect similar to that of thesemiconductor device according to the embodiment 4 shown in FIG. 22.

Steps for fabricating the semiconductor device are now described withreference to FIGS. 33 to 38.

First, steps similar to those for fabricating the semiconductor deviceaccording to the embodiment 4 of the present invention shown in FIGS. 24and 25 are carried out and thereafter a resist pattern 43 is formed on aside wall insulator film 38 and a lower surface of a buried insulatorfilm 39. This resist pattern 43 is employed as a mask for partiallyremoving the buried insulator film 39 by etching. Thus, trenches 44 a to44 f are formed.

Then, the resist pattern 43 (see FIG. 33) is removed and an insulatorfilm 56 is formed on the lower surface of the buried insulator film 39and in the trenches 44 a to 44 f, as shown in FIG. 34.

Then, a resist pattern 60 is formed on the side wall insulator film 38and the insulator film 56, as shown in FIG. 35.

Then, the resist pattern 60 is employed as a mask for partially removingthe side wall insulator film 38 by etching, as shown in FIG. 36. Thus,openings 59 a and 59 b are formed in the side wall insulator film 38.Thereafter the resist pattern 60 is removed.

Then, a silicon film 63 containing a large amount of nitrogen is formedto fill up the trenches 44 a to 44 f, as shown in FIG. 37.

Then, a flattening step is carried out for forming the fifth multi-fieldplates 40 a to 40 f having the resistive potential dividing function, asshown in FIG. 38.

Thereafter steps similar to those for the semiconductor device accordingto the embodiment 4 shown in FIGS. 30 and 31 are carried out, therebyobtaining the semiconductor device shown in FIG. 32.

(Embodiment 6)

Referring to FIG. 39, the semiconductor device is basically similar instructure to that shown in FIG. 32. In the semiconductor device shown inFIG. 39, however, an inner peripheral end 40 a of fifth multi-fieldplates having a resistive potential dividing function is electricallyconnected with an emitter electrode 16 through a polysilicon film 61 ain an inverted V-shaped isolation structure 37. An outer peripheral end40 d of the fifth multi-field plates is electrically connected with aterminal component 33 of fourth multi-field plates through a polysiliconfilm 61 b. The terminal component 33 of the fourth multi-field plates iselectrically connected with an external region 23. In more concreteterms, the emitter electrode 16 and the terminal component 33 of thefourth multi-field plates are formed to extend into openings 62 a and 62b formed by partially removing an interlayer insulator film 13 b and afield oxide film 11 b. The emitter electrode 16 is electricallyconnected with the polysilicon film 61 a on the bottom portion of theopening 62 a. Further, the terminal component 33 of the fourthmulti-field plates is electrically connected with the polysilicon film61 b on the bottom portion of the opening 62 b.

Thus, the semiconductor device having the aforementioned structure canattain an effect similar to that of the semiconductor device accordingto the embodiment 5 of the present invention shown in FIG. 32.

A buried insulator film 66 is formed in an inverted V-shaped trench.

Steps for fabricating the semiconductor device are now described withreference to FIGS. 40 to 43.

First, a trench is formed on a lower surface of an SOI layer 3 byanisotropic etching employing KOH or the like, as shown in FIG. 40. Aside wall insulator film 38 is formed on the lower surface of the SOIlayer 3 and in the trench. A polysilicon film 61 is formed on the sidewall insulator film 38. The buried insulator film 66 is formed on thepolysilicon film 61. A flattening step is carried out to obtain thestructure shown in FIG. 40.

Then, a resist pattern (not shown) is formed on lower surfaces of theside wall insulator film 38 and the buried insulator film 66. Thisresist pattern is employed as a mask for partially removing the buriedinsulator film 66, thereby forming trenches 44 a to 44 d. Thus, thestructure shown in FIG. 41 is obtained.

Then, a silicon film 63 having a high nitrogen content is formed to fillup the trenches 44 a to 44 d, as shown in FIG. 42.

Then, parts of the silicon film 63 positioned on the side wall insulatorfilm 38 are removed and a flattening step is carried out for formingfifth multi-field plate structures 40 a to 40 d (see FIG. 43).

Then, steps similar to those for the semiconductor device according tothe embodiment 4 shown in FIGS. 30 and 31 are carried out, for obtainingthe structure shown in FIG. 43.

Thereafter the field oxide film 11 b and the like are formed to obtainthe semiconductor device shown in FIG. 39.

(Embodiment 7)

Referring to FIG. 44, this semiconductor device is basically similar instructure to the semiconductor device according to the embodiment 4 ofthe present invention shown in FIG. 22. In the semiconductor deviceshown in FIG. 44, however, a forward V-shaped isolation structure 58 isformed under a field oxide film 11 b and fifth multi-field plates 40 a,40 b, 40 e and 40 f are formed also on side wall insulator films 38. Ann-type emitter diffusion region 6 is not in contact with a buried oxidefilm 2.

Insulator films 57 a to 57 f are formed on surfaces of the fifthmulti-field plates 40 a to 40 f. A polysilicon film 65 is formed to fillup the inner part of the forward V-shaped isolation structure 58.

An OFF operation of the semiconductor device shown in FIG. 44 is nowdescribed with reference to FIG. 45.

Referring to FIG. 45, the fifth multi-field plates 40 a to 40 f areformed on the bottom surface and side surfaces of the forward V-shapedisolation structure 58 in this semiconductor device. When the n-typeemitter diffusion region 6 is formed in a shallow region on a surface ofan SOI layer 3 and a potential 41 is formed to penetrate the SOI layer3, therefore, the position of an equipotential surface of the potential41 penetrating the SOI layer 3 can be adjusted for suppressing localelectric field concentration. Consequently, it is possible to preventreduction of breakdown voltage resulting from electric fieldconcentration.

Steps for fabricating the semiconductor device are described withreference to FIGS. 46 to 50.

First, a V-shaped trench is formed on the surface of the n⁻-type SOIlayer 3 having a lower surface bonded with a semiconductor substrate(not shown) provided with a buried oxide film 2 by anisotropic etchingemploying KOH or the like. The side wall insulator films 38 are formedon the surface of the SOI layer 3 and in the trench. A doped polysiliconfilm 45 is formed on the side wall insulator films 38. An insulator film55 is formed on the side wall insulator films 38. A polysilicon film 61is formed on the insulator film 55. Thereafter parts of the dopedpolysilicon film 45, the insulator film 55 and the polysilicon film 61positioned on the surface of the SOI layer 3 are removed by etching.Thus, the structure shown in FIG. 46 is obtained.

Then, a resist pattern 60 is formed on the side wall insulator films 38and the polysilicon film 61, as shown in FIG. 47.

Then, the resist pattern 60 is employed as a mask for partially removingthe polysilicon film 61, the insulator film 55 and the doped polysiliconfilm 45 by anisotropic etching, thereby forming trenches 64 a to 64 g.

Then, the resist pattern 60 is removed as shown in FIG. 49. Thepolysilicon film 61 is removed by anisotropic etching. Thus, the fifthmulti-field plates 40 a to 40 f can be formed. Insulator films 55 a to55 f remain on upper surfaces of the fifth multi-field plates 40 a to 40f.

Then, the remaining insulator films 55 a to 55 f are removed by etching.Insulator films 55 a to 55 f (see FIG. 50) such as thermal oxide filmsare formed on the surfaces of the fifth multi-field plates 40 a to 40 f.A polysilicon film 65 (see FIG. 50) is formed to fill up the trenches 64a to 64 g. Thereafter parts of the polysilicon film 65 positioned on theupper surface of the SOI layer 3 are removed by etching, to obtain thestructure shown in FIG. 50.

The structure shown in FIG. 44 can be readily obtained by forming thefield oxide film 11 b (see FIG. 44) and the like.

Referring to FIG. 44, the fifth multi-field plates 40 a to 40 f may havea resistive potential dividing function in the embodiment 7 of thepresent invention, similarly to the semiconductor device shown in FIG.39. In this case, an effect similar to that of the embodiment 6 of thepresent invention can be further attained.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

What is claimed is:
 1. An isolation structure positioned between a firstconductive region and a second conductive region formed on a majorsurface of a semiconductor substrate for isolating said first conductiveregion and said second conductive region from each other, comprising: afirst conductor formed on a position deeper than said major surface ofsaid semiconductor substrate; an insulator positioned in a directionopposite to that of the position of said first conductive region asviewed from said first conductor and formed on a position deeper thansaid major surface of said semiconductor substrate; a second conductorpositioned in a direction opposite to that of the position of said firstconductor as viewed from said insulator and formed on a position deeperthan said major surface of said semiconductor substrate; an isolationinsulator film formed on said major surface of said semiconductorsubstrate in a region Positioned on said first and second conductors andsaid insulator, a first field plate conductor film formed on saidisolation insulator film, a second field plate conductor film formed ona position close to said second conductive region from said first fieldplate conductor film at a space on said isolation insulator film, and aseparation insulator film formed between said first field plateconductor film and said second field Plate conductor film.
 2. Theisolation structure in accordance with claim 1, wherein said first andsecond conductors and said insulator are formed in a trench formed onsaid semiconductor substrate.
 3. The isolation structure in accordancewith claim 1, wherein first and second trenches having side walls areformed on said semiconductor substrate in a region between said firstconductive region and said second conductive region, said insulator isformed on said side walls of said first and second trenches, said firstconductor is formed on said insulator in said first trench, and saidsecond conductor is formed on said insulator in said second trench. 4.The isolation structure in accordance with claim 1, wherein said firstfield plate conductor film is electrically connected with said firstconductive region through a resistive element, said second field plateconductor film is electrically connected with said second conductiveregion through a resistive element, and said first field plate conductorfilm and said second field plate conductor film are electricallyconnected with each other through a resistive element.
 5. The isolationstructure in accordance with claim 4, further comprising: a firstinterlayer insulator film formed on said first and second field plateconductor films, a third field plate conductor film formed on said firstinterlayer insulator film, a fourth field plate conductor filmelectrically insulated from said third field plate conductor film andformed at a space on said first interlayer insulator film, and an upperinsulator film formed between said third field plate conductor film andsaid fourth field plate conductor film.
 6. The isolation structure inaccordance with claim 1, further comprising: a lower insulator filmformed under said semiconductor substrate, wherein said first conductiveregion is formed to be in contact with said lower insulator film.
 7. Theisolation structure in accordance with claim 2, wherein said trench hasan upper surface and a lower surface, said upper surface has a planearea smaller than that of said lower surface, and said first and secondconductors are formed on said lower surface.
 8. The isolation structurein accordance with claim 7, further comprising: an isolation insulatorfilm formed on said major surface of said semiconductor substrate in aregion positioned on said trench, wherein an end portion of said uppersurface of said trench is positioned inward beyond that of saidisolation insulator film, and an end portion of said lower surface ofsaid trench is positioned outward beyond that of said isolationinsulator film.
 9. The isolation structure in accordance with claim 7,wherein said first conductor is electrically connected with said firstconductive region through a resistive element, said second conductor iselectrically connected with said second conductive region through aresistive element, and said first conductor and said second conductorare electrically connected with each other through a resistive element.10. The isolation structure in accordance with claim 2, wherein saidtrench has an upper surface and a lower surface, said upper surface hasa plane area larger than that of said lower surface, and said first andsecond conductors are formed on said lower surface.
 11. The isolationstructure in accordance with claim 10, further comprising: third andfourth conductors formed on a side surface of said trench, and a sidewall insulator film formed between said third and fourth conductors. 12.The isolation structure in accordance with claim 10, wherein said firstconductor is electrically connected with said first conductive regionthrough a resistive element, said second conductor is electricallyconnected with said second conductive region through a resistiveelement, and said first conductor and said second conductor areelectrically connected with each other through a resistive element. 13.An isolation structure positioned between a first conductive region anda second conductive region formed on a major surface of a semiconductorsubstrate for isolating said first conductive region and said secondconductive region from each other, comprising: a resistive field platestructure; and a capacitive field plate structure being stacked on saidresistive field plate structure through an interlayer insulator film,said resistive field plate structure including: a first field plateconductor film formed between said first conductive region and saidsecond conductive region and connected with said first conductive regionthrough a resistive element; and a second field plate conductor filmelectrically connected with said first field plate conductor film andsaid second conductive region through resistive elements respectivelyand formed in the direction of the position of said second conductiveregion at a space as viewed from said first field plate conductor film,said capacitive field plate structure including: a third field plateconductor film formed between said first conductive region and saidsecond conductive region; a fourth field plate conductor filmelectrically insulated from said third field plate conductor film andformed at a space; and an insulator film positioned between said thirdfield plate conductor film and said fourth field plate conductor film;said resistive field plate structure and said capacitive field platestructure are stacked with each other through an interlayer insulatorfilm.
 14. A semiconductor device comprising the isolation structure inaccordance with claim
 1. 15. The semiconductor device in accordance withclaim 14, further comprising: a first element including said firstconductive region, and a second element including said second conductiveregion, wherein said first element is a circumferentially formedinsulated gate bipolar transistor including an emitter electrode and acollector electrode, said isolation structure is formed to enclose saidinsulated gate bipolar transistor, and said emitter electrode is formedon a region closer to the outer periphery of said circumferentiallyformed insulated gate bipolar transistor than said collector electrode.16. An isolation structure positioned between a first conductive regionand a second conductive region formed on a major surface of asemiconductor substrate for isolating said first conductive region andsaid second conductive region from each other, comprising: a firstconductor formed on a position deeper than said major surface of saidsemiconductor substrate; an insulator positioned in a direction oppositeto that of the position of said first conductive region as viewed fromsaid first conductor and formed on a position deeper than said majorsurface of said semiconductor substrate; a second conductor positionedin a direction opposite to that of the position of said first conductoras viewed from said insulator and formed on a position deeper than saidmajor surface of said semiconductor substrate; and said first and secondconductors and said insulator are formed in a trench formed on saidsemiconductor substrate, said trench having an upper surface and a lowersurface, said upper surface has a plane area smaller than that of saidlower surface, and said first and second conductors are formed on saidlower surface.
 17. The isolation structure in accordance with claim 16,wherein first and second inner trenches having side walls are formed onsaid lower surface of said trench, said insulator is formed on said sidewalls of said first and second inner trenches, said first conductor isformed on said insulator in said first inner trench, and said secondconductor is formed on said insulator in said second inner trench. 18.The isolation structure in accordance with claim 16, further comprising:an isolation insulator film formed on said major surface of saidsemiconductor substrate in a region positioned on said first and secondconductors and said insulator, a first field plate conductor film formedon said isolation insulator film, a second field plate conductor filmformed on a position close to said second conductive region from saidfirst field plate conductor film at a space on said isolation insulatorfilm, and a separation insulator film formed between said first fieldplate conductor film and said second field plate conductor film.
 19. Theisolation structure in accordance with claim 18, wherein said firstfield plate conductor film is electrically connected with said firstconductive region through a resistive element, said second field plateconductor film is electrically connected with said second conductiveregion through a resistive element, and said first field plate conductorfilm and said second field plate conductor film are electricallyconnected with each other through a resistive element.
 20. The isolationstructure in accordance with claim 19, further comprising: a firstinterlayer insulator film formed on said first and second field plateconductor films, a third field plate conductor film formed on said firstinterlayer insulator film, a fourth field plate conductor filmelectrically insulated from said third field plate conductor film andformed at a space on said first interlayer insulator film, and an upperinsulator film formed between said third field plated conductor film andsaid fourth field plated conductor film.
 21. The isolation structure inaccordance with claim 16, further comprising a lower insulator filmformed under said semiconductor substrate, wherein said first conductiveregion is formed to be in contact with said lower insulator film. 22.The isolation structure in accordance with claim 16, further comprising:an isolation insulator film formed on said major surface of saidsemiconductor substrate in a region positioned on said trench, whereinan end portion of said upper surface of said trench is positioned inwardbeyond that of said isolation insulator film, and an end portion of saidlower surface of said trench is positioned outward beyond that of saidisolation insulator film.
 23. The isolation structure in accordance withclaim 16, wherein said first conductor is electrically connected withsaid first conductive region through a resistive element, said secondconductor is electrically connected with said second conductive regionthrough a resistive element, and said first conductor and said secondconductor are electrically connected with each other through a resistiveelement.
 24. A semiconductor device comprising the isolation structurein accordance with claim
 16. 25. The semiconductor device in accordancewith claim 24, further comprising: a first element including said firstconductive region, and a second element including said second conductiveregion, wherein said first element is a circumferentially formedinsulated gate bipolar transistor including an emitter electrode and acollector electrode, said isolation structure is formed to enclose saidinsulated gate bipolar transistor; and said emitter electrode is formedon a region closer to the outer periphery of said circumferentiallyformed insulated gate bipolar transistor than said collector electrode.26. An isolation structure positioned between a first conductive regionand a second conductive region formed on a major surface of asemiconductor substrate for isolating said first conductive region andsaid second conductive region from each other, comprising: a firstconductor formed on a position deeper than said major surface of saidsemiconductor substrate; an insulator positioned in a direction oppositeto that of the position of said first conductive region as viewed fromsaid first conductor and formed on a position deeper than said majorsurface of said semiconductor substrate; a second conductor positionedin a direction opposite to that of the position of said first conductoras viewed from said insulator and formed on a position deeper than saidmajor surface of said semiconductor substrate; and said first and secondconductors and said insulator are formed in a trench formed on saidsemiconductor substrate, said trench has an upper surface and a lowersurface, said upper surface has a plane area larger than that of saidlower surface, and said first and second conductors are formed on saidlower surface.
 27. The isolation structure in accordance with claim 26,wherein said first and second inner trenches having side walls areformed on said lower surface of said trench, said insulator is formed onsaid side walls of said first and second inner trenches, said firstconductor is formed on said insulator in said first inner trench, andsaid second conductor is formed on said insulator in said second innertrench.
 28. The isolation structure in accordance with claim 26, furthercomprising: an isolation insulator film formed on said major surface ofsaid semiconductor substrate in a region positioned on said first andsecond conductors and said insulator, a first field plate conductor filmformed on said isolation insulator film, a second field plate conductorfilm formed on a position close to said second conductive region fromsaid first field plate conductor film at a space on said isolationinsulator film, and a separation insulator film formed between saidfirst field plate conductor film and said second field plate conductorfilm.
 29. The isolation structure in accordance with claim 28, whereinsaid first field plate conductor film is electrically connected withsaid first conductive region through a resistive element, said secondfield plate conductor film is electrically connected with said secondconductive region through a resistive element, and said first fieldplate conductor film and said second field plate conductor film areelectrically connected with each other through a resistive element. 30.The isolation structure in accordance with claim 29, further comprising:a first interlayer insulator film formed on said first and second fieldplate conductor films, a third field plate conductor film formed on saidfirst interlayer insulator film, a fourth field plate conductor filmelectrically insulated from said third field plate conductor film andformed at a space on said first interlayer insulator film, and an upperinsulator film formed between said third field plated conductor film andsaid fourth field plated conductor film.
 31. The isolation structure inaccordance with claim 26, further comprising: a lower insulator filmunder said semiconductor substrate, wherein said first conductive regionis formed to be in contact with said lower insulator film.
 32. Theisolation structure in accordance with claim 26, further comprisingthird and fourth conductors formed on a side surface of one of saidtrench, and a side wall insulator film formed between said third andfourth conductors.
 33. The isolation structure in accordance with claim26, wherein said first conductor is electrically connected with saidfirst conductive region through a resistive element, said secondconductor is electrically connected with said second conductive regionthrough a resistive element, and said first conductor and said secondconductor are electrically connected with each other through a resistiveelement.
 34. A semiconductor device comprising the isolation structurein accordance with claim
 26. 35. The semiconductor device in accordancewith claim 14, further comprising: a first element including said firstconductive region, and a second element including said second conductiveregion, wherein said first element is a circumferentially formedinsulated gate bipolar transistor including an emitter electrode and acollector electrode, said isolation structure is formed to enclose saidinsulated gate bipolar transistor; and said emitter electrode is formedon a region closer to the outer periphery of said circumferentiallyformed insulated gate bipolar transistor than said collector electrode.